NXP Semiconductors /MIMXRT1052 /CAN1 /ESR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ESR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IMB_0)IMB 0 (VPS_0)VPS 0LPTM

IMB=IMB_0, VPS=VPS_0

Description

Error and Status 2 Register

Fields

IMB

If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000)

0 (IMB_0): If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.

1 (IMB_1): If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

VPS

This bit indicates whether IMB and LPTM contents are currently valid or not

0 (VPS_0): Contents of IMB and LPTM are invalid

1 (VPS_1): Contents of IMB and LPTM are valid

LPTM

If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description)

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